As it is well known, for the electric selection of devices carried out on wafer, i.e., the so called testing EWS (acronym of “Electrical-Wafer-Sorting”), it is typically necessary to electrically couple a tester or ATE (acronym of “Automated Test Equipment”) that executes measures on a wafer whereon there are electronic components to be tested or selected or evaluated, in particular integrated circuits or chips. A terminal portion of the testing apparatus is schematically shown in FIG. 1A, globally indicated with 1.
The interface between the real tester ATE 1A and a wafer 6 includes a plurality of devices to be tested or selected, in particular chips 7 (also indicated as integrated circuits or IC, acronym of “Integrated Circuit”) is a so called probe card 2, which is a board including in substance a PCB (acronym of “Printed Circuit Board”) and a probe head 3 that in turn includes different e.g., hundreds or thousands) of probes 4 that electrically couple the tester ATE 1A to all, or almost all, the contact pads 8 of a chip 7 to be tested, as shown in greater detail in FIG. 1B. In particular, each end portion or tip 9 of the probes 4 comes into contact with a contact pad 8 of the chip 7 during a testing phase.
In general, the wafer 6 groups a plurality of chips 7 to be tested, and during the testing steps it is put on a support called chuck 5, shown in the portion of the testing apparatus 1, and belonging to an apparatus also called prober (not shown in the figure), this support 5 being thus also indicated as a prober chuck.
The number of contact pads 8 necessary for a determined testing may be smaller or equal to the total number of contact pads 8 of the chip 7 to be tested.
One may test in a similar way even if the chips 7 have contact bumps instead of contact pads 8.
Before each chip 7 is encapsulated in a corresponding package, it is known to execute the testing of the chip 7 itself, being still on the wafer 6, using the probes 4 that are directly coupled to the contact pads 8, and that thus execute the so called probing of the contact pad 8 they come in contact with.
After the testing, the wafer 6 is cut (a process referred to as “singulation”) and the chips 7 that have been tested and are determined to be properly operating are assembled in their package, ready for further process steps, also including final test steps of the chips 7 in the package wherein they have been assembled.
To this purpose, on the wafer 6, between one chip 7 and another, an area called a scribe line SL is created within which a saw or a laser will pass during the cutting or singulation operation, necessary for separating the various devices being on the wafer for executing the various assembling and encapsulating or packaging steps of the same devices, as schematically shown in FIG. 2. In particular, in the schematic enlargement indicated by way of illustration in FIG. 2, a group of four chips 7, indicated as IC A, IC B, IC C and IC D, are separated by a first scribe line SL1, in particular with a horizontal orientation according to the local reference of the figure, and a second scribe line SL2, in particular with a vertical orientation in the local reference of the figure.
Moreover, as shown in this figure, in the scribe lines (in particular in the first scribe line SL1) elementary structures are sometimes introduced, usually indicated as structures TEG (acronym of “Test Element Group”), these structures being used, for example, for the testing of some process parameters, that are in general measured before the electric wafer test EWS.
The structures TEG are, in general, coupled to pads being also in the scribe line SL and normally distinct with respect to the pads of the chip 7.
It is also known from U.S. Pat. No. 7,224,176, which is incorporated by reference, to realize a wafer wherein the pads of the structures TEG coincide with the pads of the chips.
In practice, however, such a realization has problems in the operation since the structures TEG thus coupled suffer from the effect of the circuits being in the chips and from their faults. In particular, there may be problems tied to leakage currents in the chip or in the pads shared by chips and structures TEG that may be, for example, in short circuit with the ground.
Furthermore, in the case in which the structures TEG are used for understanding the manufacturing process problems of the wafer, it may be difficult to execute reliable and accurate measures by using pads shared by chips and structures TEG, due to the presence of defects in the chip itself on the wafer due to the process problems.
The circuits realized on the chips also introduce parasitics (e.g., resistances, capacitances, non-linear effects, etc.) that may jeopardize the accuracy of the measurement on the structures TEG.
Furthermore, each chip 7 is surrounded by a conventional protection structure, the so called seal ring 7A.
More in particular, the seal ring 7A has the aim of sealing the respective chip 7 and mechanically strengthening it for ensuring the reliability and protection against the mechanical effort exercised by the saw during the cutting or singulation of the chip 7 from the wafer 6.
The seal ring 7A is usually placed between an area where the contact pads of the chip itself are placed, normally indicated as pad ring, and the scribe line confining with the chip itself.
Usually, the seal ring 7A includes a plurality of metal layers and of vias that couple them so as to realize a structure able to block also ions and polluting substances (such as for example humidity) that could jeopardize the good operation of the chip 7 after the singulation.
Different implementations are known for the realization of a seal ring of an integrated electronic device or chip. For example, in U.S. Pat. No. 6,300,223, which is incorporated by reference, a structure of a seal ring is described wherein dielectric layers and metal layers are alternated, the structure being also provided with a trench for reducing the mechanical stresses at the singulation of the chips from the wafer. Other structures suitable for realizing a seal ring are also known from U.S. Pat. Nos. 7,605,448 and 6,492,716, which are incorporated by reference.
For avoiding the problems of radiofrequency interferences being able to jeopardize the operation of the chip, it is also known to suitably cut the seal ring in those points whereat substrate disturbances could be injected coming from internal circuits of the chip itself (such as power amplifiers, clock signals generators, processing circuits of input/output digital signals, etc).
The growing requests for electronic applications able to sustain higher and higher temperatures have also brought the introduction of new materials for realizing the pads and the couplings between the pads and the package of the chips so as to ensure a good electric coupling.
Some of these materials are also used for strengthening the pad itself. For example, it is possible to use surface covering layers realized in materials with greater hardness with respect to those traditionally used, such as for example aluminum, avoiding in this way breaking the possible microelectronic structures being under the pad.
A pad made of some layers of different materials able to improve the strength of the pad as a whole is described for example in United States Patent Application Publication No. 2005/0073057, which is incorporated by reference.
In this case, a generic pad 8 of a chip includes for example an upper metal layer corresponding to a final metal layer of the chip wherein this pad is realized and made of a generic material A (for example copper). According to the teaching of United States Patent Application Publication No. 2005/0073057, above the material A there is presented a first material B having a high hardness (for example nickel or an alloy thereof) and a second material C (for example palladium or an alloy thereof). Possibly, another layer of a further material D (for example gold or an alloy thereof) may be realized above the second material C, the pad being also surrounded by a passivation layer E, as schematically shown in FIG. 3 of the present patent application.
Between the materials A and B, as well as between the materials B and C and between the materials C and D, there may possibly be also layers of still other materials, created one above the other using known techniques in the field of the manufacturing of integrated circuits.
For example, one of the known techniques for the growth of these materials is the so called electroless process, the considerations that follow being however valid also for other types of processes.
In particular, further to the growth and/or deposition of the materials according to the process used, these same materials will be present on all the pads 8 of the wafer 6, and in particular on the pads of the chips 7 but also on the pads of the structures TEG.
After the testing of these structures TEG and of the chips 7 of the wafer, the wafer itself is cut and the working devices are assembled in a package.
The presence of the hard materials on the pads of the structures TEG makes it however difficult to execute the cut or singulation of the chips 7 from the wafer 6, executed as already said by means of a diamond saw, for example. In this case in fact, the saw may damage the edge of the chip 7 exactly because of the presence of hard materials on the pads of the structures TEG, thus creating chippings.
Solutions currently known do not allow then to execute measures in an accurate and reliable way of the structures TEG. In particular, these measures are not reliable in the case of shared pads by the structures TEG and the chips 7 that surround them. Further problems introduced by the presence of the seal ring, that requires the use of complex structures aimed at crossing it, that contribute to the increase of the final costs of the chips thus obtained. Finally, the presence of hard materials aimed at strengthening the structures of the pad also on the surface of the pads of the structures TEG introduces problems of chipping of the chip at their singulation from the wafer wherein they have been realized.